1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to semiconductors including field effect transistors and non-volatile information storage areas.
2. Description of the Related Art
Integrated circuits typically comprise a very large number of circuit elements on a given chip area according to a specified circuit layout, wherein advanced devices may comprise millions of signal nodes that may be formed by using field effect transistors, which may also be referred to herein as MOS transistors. Thus, field effect transistors may represent a dominant component of modern semiconductor products, wherein advances towards increased performance and low integration volume are mainly associated with a reduction of size of the basic transistor structures. Generally, a plurality of process technologies are practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of field effect transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions represented by an interface formed of highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer.
Due to the reduced dimensions of circuit elements, not only performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated microcontroller devices and other complex circuits, an increasing amount of storage capacity may be provided on chip, thereby also significantly enhancing the overall performance of complex electronic systems. Similarly, in many types of control circuits, different types of storage devices may be incorporated so as to provide an acceptable compromise between die area consumption and information storage density on the one side versus operating speed on the other side. For instance, fast or temporary buffer memories, so-called cache memories, may be provided in the vicinity of the CPU core, wherein respective cache memories may be designed so as to allow reduced access times compared to external storage devices.
On the other hand, increasingly, non-volatile memories may have to be incorporated in sophisticated semiconductor devices, wherein the flash memory technique represents one promising technology, in which MOS technology may be efficiently applied to forming storage cells. To this end, basically a field effect transistor is provided, in which transistor operation is controlled, on the other hand, by a gate electrode, as discussed above, which additionally includes a “floating” gate that is electrically insulated from the control gate electrode and from the channel region and drain region of the field effect transistor. The floating gate represents a dielectric charge storage region within the control gate electrode of the field effect transistor and may hold “stationary” charge carriers, which in turn influence the current flow behavior of the field effect transistor. The stationary charge carriers in the floating gate may be injected upon establishing a specific operation mode, which is also referred to as programming of the memory cell, in which any type of leakage current generating mechanism may be taken advantage of so as to result in the incorporation of charge carriers in the charge storage region. Consequently, in the normal operation mode, the injected charge carriers in the charge storage region may thus significantly affect the current flow through the channel region of the transistor, which may be detected by an appropriate control circuitry. On the other hand, upon “erasing” the memory cell, the charge carriers in the charge storage region may be removed, for instance by establishing appropriate voltage conditions, thereby establishing a detectable different operational behavior of the field effect transistor during the normal operation mode, i.e., during the operation with the standard supply voltages. Although the concept of flash memory cells, i.e., of field effect transistors comprising a floating gate, provides a non-volatile storage mechanism with moderately high information density and short access times, it turns out that still significant drawbacks, such as relatively long write times and complex erase cycles, in combination with reduced durability of the storage mechanism, may render this approach less attractive, in particular in combination with fast logic circuit elements, such as sophisticated high-k metal gate based transistors.
In addition to flash memory devices, other concepts have been the subject of intensive investigations in order to provide non-volatile memory devices. In this respect, ferroelectric materials have been investigated, since ferroelectricity may generally represent a very attractive concept for implementing a non-volatile memory. For example, highly efficient capacitors may be formed on the basis of a ferroelectric dielectric material, wherein the polarization state of the ferroelectric material may be adjusted on the basis of appropriate electrical fields applied to the ferroelectric material in order to “program” the capacitor. Since the polarization state may be preserved unless a corresponding high electrical field or a high temperature is applied, the information reflected by the polarization state may thus be preserved upon switching off the supply power for the capacitor. Hence, contrary to conventional storage capacitors, a refreshment of the state of the capacitor is not required. Therefore, a capacitor formed on the basis of a ferroelectric dielectric material may not only provide a non-volatile device, but also superior performance compared to conventional capacitors.
Moreover, with respect to further reducing the required chip area, a field effect transistor may be formed on the basis of a ferroelectric gate dielectric material, thereby achieving stable transistor states upon appropriately adjusting the polarization of the ferroelectric gate dielectric material. That is, depending on the polarization state, significantly different drive current/gate voltage characteristics are obtained, which may thus be used for defining different logic state. Also in this case, the polarization state is stable, unless a sufficiently high voltage and/or a high temperature is applied, so that the field effect transistor itself may be used as a non-volatile memory cell.
Although a ferroelectric field effect transistor or a ferroelectric capacitor represents a very promising concept for a non-volatile storage device, it has proven to be a difficult task to identify appropriate ferroelectric materials, in particular when ferroelectric components, such as ferroelectric field effect transistors, are to be combined with sophisticated transistor structures as are typically used in complex logic circuitry. Recent research results, however, indicate that hafnium oxide-based dielectric materials may represent promising candidates for materials providing ferroelectric behavior. For example, in Boescke et al., “Ferroelectricity in Hafnium Oxide: CMOS compatible Ferroelectric Field Effect Transistors,” IEDM 2011 (the entire disclosure of which is incorporated herein by reference), silicon dioxide doped hafnium oxide has been identified as a material, for which an appropriate crystalline state may be established that provides the ferroelectric behavior. Consequently, circuit elements, such as field effect transistors, capacitors and the like, may be formed on the basis of silicon dioxide doped hafnium oxide in order to provide superior functionality of complex integrated circuits, for instance with respect to exploiting the ferroelectric behavior so as to form a non-volatile storage element. On the other hand, the above-identified document does not relate to process techniques and semiconductor devices, in which sophisticated transistors as are typically used for logic circuitry may be provided in combination with ferroelectric circuit elements.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices including ferroelectric circuit elements, in particular ferroelectric field effect transistors, while avoiding or at least reducing the effect of one or more of the problems identified above.